1. Field of the Invention
The present invention generally relates to a gate array integrated circuit and, more particularly, to a gallium arsenide (GaAs) gate array integrated circuit employing direct-coupled field effect transistor logic gates (DCFL).
2. Description of the Prior Art
In basic logic gates of a GaAs digital IC, a buffered FET Logic (referred to as "BFL"), Schottky Diode FET Logic (referred to as "SDFL") and direct-coupled FET Logic (referred to as "DCFL"), etc. are known in the art. A NAND gate, NOR gate and INVERTER are constituted by either normally-on type FET's (referred to as "D-FET"), or normally-off type FET's (referred to as "E-FET"). These conventional logic gates are disclosed, for instance, in IEEE Transactions on Electron Devices, Vol. ED-31, No. 2, page 144, entitled "A Gallium Arsenide SDFL Gate Array with On-Chip RAM" by THO T. VU. et al. (February, 1984) and IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, page 728, entitled "A Gallium Arsenide Configurable Cell Array Using Buffered FET Logic" by R. N. Deming et al. (October, 1984), and IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, page 721, entitled "A 1K-Gate GaAs Gate Array" by Y. Ikawa et al. (October 1984).
In these types of logic gates, power consumption per gate greatly differs from type to type. Typically, BFL consumes several milliwatts (mW) to several tens of mW and SDFL consumes 1 mW to several mW, while DCFL consumes only several hundred microwatts (.mu.W) per gate. The reason for this is as follows. In both BFL and SDFL employing only the normally-on FETs (D-FET), a level shift circuit, which dissipates undesirable power, is necessarily required. In DCFL, on the other hand, no level shift circuit is needed because the normally-off type FET (E-FET) is directly coupled in DCFL.
Consequently, in order to assemble more than one thousand logic gates in a GaAs-LSI (Gallium Arsenide-Large Scale Integration), no other suitable solutions have been known in the art in view of power consumption but to employ DCFL.
In a GaAs integrated circuit, it is not possible to employ a MOS-FET such as in a silicon integrated circuit and, therefore, FET is restricted to a junction type FET (a pn junction or a Schottky junction type). In view of the integrated circuit manufactured using a silicon substrate, the Schottky junction type is used from the standpoint of the high-speed operation and fine construction requirements. As a DCFL using the Schottky junction type FET's is operated in such a mode as to apply a forward bias across the gate and source of a driver FET, a high logic level is clamped at a forward raising voltage level on the Schottky junction. For this reason, a logical level of typical DCFL is as small as about 0.6 V and a typical noise margin thereof is as small as about 0.2 V.
Now suppose that a NAND gate is constructed by the conventional method using a DCFL of a smaller logical level. FIG. 1 is one form of such a circuit arrangement. 61 denotes a load FET made of D-FET; and 62, 63 are driver FET's made of E-FETs. When in this case the driver FET 63 on the ground line side is in an ON state, the source voltage of the driver FET 62 on the load side is further increased by a voltage drop defined by the series resistance times the source-to-drain current. This series resistance is the resistance of the source-to-drain path of the driver FET when turned on. As a result, a noise margin on the low level side becomes very small and stable operation for the NAND gate can be hardly expected.
In the GaAs logic integrated circuit using the DCFL circuit, therefore, a NOR gate circuit is mainly constructed by a load FET 71 and a parallel circuit of two driver FET's 72 and 73 as shown in FIG. 2. It has been normally known that the NAND circuit can be comprised of a combination of a NOR gate and inverter. In this known arrangement, an occupation area in the whole IC pattern due to the use of two logic stages of gates (and thus an increased number of gates) is increased, as well as an operation time is delayed and thus a NAND gate of a single stage configuration is required. Since in the gate array integrated circuit the size and pattern of its basic cell are previously determined, it is undesirable from the standpoint of the wafer availability to prepare various sizes of FET's, resulting in impairing its inherent excellent characteristics.
FIG. 3 shows one pattern of a basic cell layout of a GaAs gate array of a typical DCFL (as disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, No. 5 October, 1984 "A 1K-Gate GaAs Gate Array" by Y. Ikawa et al. FIG. 7a). In the basic cell 81 shows a D-FET serving as a load, and 82, 83 and 84 show E-FETs working as a driver. Connecting E-FETs 82, 83 and 84 in parallel configuration with the use of such a basic cell provides a 3-input NOR gate as shown in FIG. 4. In the layout of FIG. 3 the respective FETs 82, 83 and 84 are connected to the ground line "GND" as indicated by a broken line 85.
It is, however, difficult to constitute a GaAs NAND gate for DCFL, using the single basic cell as set out above, i.e., with no need of using an increased number of logic stages.
A primary object of this invention is to provide a GaAs gate array integrated circuit which permits the use of a stably operated NAND gate employing an optimally integrable DCFL and the full use of a basic cell in view of the entire wafer area.
Another object of this invention is to provide a GaAs gate array integrated circuit comprised of NAND gates having a lower signal delay.